This application claims the priority of Korean Patent Application No. 2003-35606, filed on Jun. 3, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
This disclosure relates to a multi-port memory device, and more particularly, to a multi-port memory device in which each of stacked banks is operated independently.
2. Description of the Related Art
In a general dual-port memory device, a pair of data is read from a memory cell array through an output port and simultaneously is written to the memory cell array through an input port. Such a dual-port memory device can be used as a video memory device for video cameras, etc. However, since the dual-port memory device has a limited number of ports allowing simultaneous access, a multi-port memory device capable of reserving a required number of ports as necessary is required to achieve high-functionality and high definition.
The multi-port memory device performs a bank access operation independently through a multi-channel. An operation speed of the multi-port memory device is dependent on the independent bank access operation and independent reading and writing operations. The independent reading and writing operations are closely related to a data line structure in the multi-port memory device.
FIG. 1 is a view for explaining an internal structure of a conventional multi-port memory device. Referring to FIG. 1, a multi-port memory device 10 includes a number of banks bank0 100, bank1 101, bank2 102, and bank3 103; data line sense amplifiers IO SA 110 and IO SA 112; data line drivers IO DRV 120 and IO DRV 122; write buffers 130, 132, 134, and 136; read buffers 140, 142, 144, and 146; and a number of ports port0 150, port1 152, port2 154, and port3 156. The bank0 100, bank1 101, bank2 102, and bank3 103 form a stacked bank structure. Multi-bit data, for example, 512 bit data is input or output through the ports 150, 152, 154, and 156.
The bank0 100 and bank1 101 are connected to a first data line sense amplifier 110 or a first data line driver 120 through first global data lines GIO<i>, i=0, 1, 2, . . . , 511. The bank2 102 and bank3 103 are connected to a second data line sense amplifier 112 or a second data line driver 122 through second global data lines GIO<j>, j=0, 1, 2, . . . , 511. The data line sense amplifiers 110 and 112 are connected to the read buffers 140, 142, 144, and 146 through read data lines RDL. The read buffers 140, 142, 144, and 146 are connected to the ports 150, 152, 154, and 156, respectively. The data line drivers 120 and 122 are connected to the write buffers 130, 132, 134, and 136 through a write data line WDL. The write buffers 130, 132, 134, and 136 are connected to the ports 150, 152, 154, and 156, respectively.
The reading and writing operations of the multi-bank memory device 10 having the above-described structure are described below. FIG. 2 is a block diagram for explaining a read data path of the multi-bank memory device 10. Referring to FIG. 2, 512 bit memory cell data read form the bank0 100 and bank1 101 is transferred to the first data line sense amplifier 110 through first global data lines GIO<0>, GIO<1>, GIO<2>, . . . , GIO<511>. 512 bit memory cell data read from the bank2 102 and bank3 103 is transferred to the second data line sense amplifier 112 through the second global data lines GIO<0>, GIO<1>, GIO<2>, . . . , GIO<511>. The first data line sense amplifier 110 and the second data line sense amplifier 112 share read data lines RDL<0>, RDL<1>, RDL<2>, . . . , RDL<511>.
Since the first and the second data line sense amplifiers 110 and 112 share the read data lines RDL, only one of the first and the second data line sense amplifiers 110 and 112 is selectively connected to the read buffers 140, 142, 144, and 146. If the first data line sense amplifier 110 is connected to the read data lines RDL<0>, RDL<1>, RDL<2>, . . . , RDL<511>, the 512 bit memory cell data selected in the bank0 100 and bank1 101 is sensed and amplified by the first data line sense amplifier 110 and is stored in one of the read buffers 140, 142, 144, and 146. For example, it can be stored in the first read buffer 150 through the read data lines RDL<0>, RDL<1>, RDL<2>, . . . , RDL<511>. The 512 bit data stored in the first read buffer 140 can then be sequentially output through the port0 150.
Here, while the memory cell data read from the bank0 100 and bank1 101 is accessed and is output through the read buffer 140 and the port0 150, memory cell data of the bank2 102 and the bank3 103 cannot be accessed.
FIG. 3 is a block diagram for explaining a write data path of the multi-port memory device shown in FIG. 1. Referring to FIG. 3, similar to the read data path of FIG. 2, for example, write data received through the port0 150 is sequentially stored in a first write buffer 130 and constructs 512 bit data. The 512 bit data stored in the first write data buffer 130 is transferred, for example, to a first data line driver 120 through write data lines WDL<0>, WDL<1>, WDL<2>, . . . , WDL<511>. The first data line driver 120 is connected to the bank0 100 or bank1 101 through the global data lines GIO<0>, GIO<1>, GIO<2>, . . . , GIO<511>, and stores the write data in a selected bank, for example, in the 512 memory cells of the bank0 100.
Similar to the read operation, while the write data received through the port0 150 and the write buffer 130 is accessed to the memory cells of the bank0 100 or the bank1 101 and is stored therein, the write data cannot access the memory cells of the bank2 102 and bank3 103.
As described above, since in the conventional multi-port memory device 10, the stacked bank0 100 and bank1 101, and the bank2 102 and bank3 103 cannot be accessed independently, a limitation exists in a data read speed and data write speed. For this reason, a multi-port memory device having a stacked bank structure allowing independent access and capable of performing independent reading and writing operations is necessary.
Embodiments of the invention address these and other limitations in the prior art.